A low-latency real-time PAM-4 receiver enabled by deep-parallel technique

High-speed photonic networks using digital signal processing (DSP) techniques are flourishing nowadays to meet the high-bandwidth requirements of modern bandwidth-thirsty applications in a cost-effective manner. However, additional latency introduced by DSP is hindering latency-critical applications. In this paper, FPGA-based real-time low-latency four-level pulse amplitude modulation (PAM-4) receiver including adaptive equalization (DAE) designed and implemented latency-reducing parallel architecture. The DSP-introduced end analyzed detail. As for DAE implementation, novel re-allocation scheme proposed cope with issue dependency output on successive input samples, look-ahead computation technique improve update efficiency. A PAM-4 demonstrated an experimental fiber link 2.5 Gbit/s data rate performance evaluation. Compared offline MATLAB, BER has little deterioration at 7% FEC limit 1 × 10−3. With help deep-parallel technique, reduced 0.4μs average, which better meets latency-sensitive user cases 5G networks. Furthermore, could be flexibly reconfigured various scenarios requirements, latency-efficient as well analysis method can also extended high-speed hardware implementation rates up 100 or more.